芯片设计工程师- Core

招聘人数：1-3人 到岗时间：不限 年龄要求：不限 性别要求：不限 婚况要求：不限 Responsibilities:

Array architecture development, circuit design an d physical design.Page/block/plane configuration an d redundancy design.Power/performance/die size optimization for array operations.User modes an d test modes design.Array pitch cell physical design an d revision.Sense Amplifier operation analysisand page buffer design.Wordline-related bias/timing design. Core operation noiseanalysis,power, an d ground network analysis.Average/Peak power planning an d optimization.Memory reliability analysis with different design options.Floor-planning, layout guideline an d layout checking.Block an d fullchip level design, simulation, pre/post layout verification,User modes an d test modes design an d validation.Various tape-out checks （IR/EM/etc） at block-level an d fullchip-level.Silicon characterization an d debugging: FIB, micron-probing, failure analysis, problem-solving an d mask revision.
任职要求:

国内外知名大学电子工程或微电子专业硕士学位，有经验者学历可适当放宽；3~10年工作经验有很强的晶体管级CMOS电路设计和器件物理背景；熟练使用相关EDA工具有存储器相关设计经验者优先，有DRAM设计经验者优先。